RV64I Instruction Set Simulator

 

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

 

Github:   https://github.com/LevyHsu/RV64I-ISS

RISC-V Foundation:   https://riscv.org/

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An instruction set simulator (ISS) for the RV64I subset of the RISC-V instruction set.

All error-handling related instructions ( including implementation for CSR register ) will be post later.

parent directory
rv64sim
tests

– command_tests
– harness_tests
– instruction_tests
– compiled_tests

Debug with “-v” flag

 

make

$make

 

command_tests

$./rv64sim < command_test_m.cmd

 

instruction tests

$./run_test instruction_test_add

or

$./run_instruction_tests

 

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Support instruction list:

 

RV32I Base Instruction Set:

LUI AUIPC JAL JALR BEQ BNE BLT BGE BLTU BGEU LB LH LW LBU LHU SB SH SW ADDI SLTI SLTIU XORI ORI ANDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI ADD SUB SLL SLT SLTU XOR SRL SRA OR AND

 

RV64I Base Instruction Set (in addition to RV32I):

LWU LD SD SLLI SRLI SRAI ADDIW SLLIW SRLIW SRAIW ADDW SUBW SLLW SRLW SRAW

 

CSR Register:

0xF11 Mevendorid
0xF12 Marchid
0xF13 Mimpid
0xF14 Mhartid
0x300 Mstatus
0x301 Misa
0x304 Mie
0x305 Mtvec
0x340 Mscratch
0x341 Mepc
0x342 Mcause
0x343 Mtval
0x344 Mip

 

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