This bug was initially raised by one of the developers on GCC Bugzilla https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 Where for a simple volatile load/store like: gcc will generate: However, the definition of lbu from RISC-V spec mentioned: ” The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd… Read more [GCC] RISC-V: Avoid zero/sign extend for volatile loads.