Category: gcc

[GCC] RISC-V: Add patterns for builtin overflow.

Posted on by [email protected]

This patch has been committed to the master branch: https://gcc.gnu.org/pipermail/gcc-patches/2021-April/569135.html https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6efd040c301b06fae51657c8370ad940c5c3d513 Learn more about Built-in Functions about Performing Arithmetic with Overflow Checking: https://gcc.gnu.org/onlinedocs/gcc/Integer-Overflow-Builtins.html Since these functions are pervasively used in the kernel, driver, etc. Adding patterns to the RISC-V backend should allow us to have some performance elevation. Some example: https://android.googlesource.com/kernel/common.git/+/refs/tags/ASB-2019-03-05_4.9/include/linux/overflow.h https://lwn.net/Articles/623368/ Let’s start with… Read more [GCC] RISC-V: Add patterns for builtin overflow.

[GCC] RISC-V: Avoid zero/sign extend for volatile loads.

Posted on by [email protected]

This bug was initially raised by one of the developers on GCC Bugzilla https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417 Where for a simple volatile load/store like: gcc will generate: However, the definition of lbu from RISC-V spec mentioned: ” The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd… Read more [GCC] RISC-V: Avoid zero/sign extend for volatile loads.